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The present invention relates to computer-assisted methods and apparatus for generating electronic designs such as designs for digital integrated circuits. More specifically, the invention relates to improvements in the usefulness of xe2x80x9coff-the-shelfxe2x80x9d functional blocks for electronic designs.
Present Electronic Design Automation (EDA) systems for the design of electronic circuits, sometimes referred to as ECAD or electronic CAD systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer. Such systems are provided with various architectures. In one widely used architecture, five major software program functions run on the ECAD system: a schematic editor, a compiler, a simulator, a verifier, and a layout program. Sometimes, the layout program forms part of the compiler. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram of an electronic design using the display screen, generating a net list (summary of connections between components) in the process. An equivalent method for entering an electronic design involves providing a description of the design in a Hardware Description Language (HDL). Examples of HDLs include Verilog and VHDL. The syntax of a VHDL description is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987), which is incorporated herein by reference for all purposes and in its entirety. Like the schematic representation, the HDL representation also provides a net list.
The compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification, and simulation into an object file or files. The verifier checks the input design (schematic or HDL) for design errors, such as multiple outputs connected together, overloaded signal paths, etc. and generates error indications if any such design problems exist. The simulator takes the object file(s) and simulation models, and generates a set of simulation results, acting on instructions, initial conditions, and input signal values provided to it either in the form of a file or user input.
Often a designer creates an electronic design from various functional blocks. For example, the designer may first create a functional block for a particular filter, then create a functional block for a buffer, and then one for a memory block, and so on. With the component functional blocks in hand, the designer makes the necessary connections between them to create the larger design, a project. It is often convenient to design reusable functional blocks for use in multiple electronic designs/projects. For example, a functional block that performs the computationally intensive steps of a fast Fourier transform or an inverse fast Fourier transform may find use in many integrated circuits (e.g., circuits for encoding and decoding audio and video information digitally and analyzing data from various scientific instruments). Various individuals and groups developing relevant electronic designs have created reusable functional blocks for fast Fourier transforms and inverse fast Fourier transforms.
A user simply inserts the functional block into his or her larger electronic design, makes the necessary connections to other features of the larger electronic design, and compiles the entire design per the normal procedure. The resulting compiled electronic design includes the off-the-shelf functional block integrated with other components of the design in a compiled form. This design can be then used to program a programmable logic device or layout an application specific integrated circuit (ASIC), for example. Such predefined off-the-shelf functional blocks are given various names in the EDA industry. Examples include megafunctions, cores, macrofunctions, and the like. For convenience, any such functional blocks will often be referred to herein as xe2x80x9cmegafunctionsxe2x80x9d or simply xe2x80x9cfunctional blocks.xe2x80x9d
The underlying design associated with a megafunction will be defined by various parameters. Examples include bus widths, buffer sizes, memory array dimensions, etc. Many megafunctions contain rigidly set values for the associated parameters. For example, a buffer functional block may require a buffer depth of 16 words and a buffer width of 32 bits. Unfortunately, this rigidity limits wide spread use of such megafunctions. While many users may need a particular type of buffer, only a small fraction of them can make use of functional blocks that specify a particular bus width or buffer size. Functional blocks having such rigidly set specifications arc frequently referred to as xe2x80x9cnon-parameterizedxe2x80x9d functional blocks or megafunctions.
To address the difficulty of non-parameterized megafunctions, xe2x80x9cparameterizedxe2x80x9d megafunctions have been developed. Typically, these megafunctions take advantage of the ability of some Hardware Description Languages to encode parameters for which the user/developer can specify values. Collections or libraries of parameterized megafunctions are available. One example is the library of parameterized modules (xe2x80x9cLPMxe2x80x9d) developed under the guidance of the EDIF association. Examples of members of the library include adders, multipliers, comparators, etc. Generally, these functions are rather low level.
Unfortunately, there are various problems with these parameterized megafunctions. For many of the various Hardware Description Languages available, parameterization is a poorly developed feature. This may be because most Hardware Description Languages were designed for simulation, not design entry and synthesis. As a result, parameterization is not supported universally and fully in many Hardware Description Languages. The proprietary Hardware Description Language, AHDL, used to design programmable logic devices of Altera Corporation (San Jose, Calif.), does fully support parameterization. Thus, parameterized megafunctions written in AHDL may have a rich compliment of parameterization. Unfortunately, similar megafunctions written in other Hardware Description Languages such as VHDL or Verilog, typically cannot have the rich compliment of parameterization available in AHDL megafunctions. Unfortunately, non-proprietary Hardware Description Languages such as VHDL and Verilog are widely used in the industry.
What is needed therefore is an improved method of providing flexibility to a user in selecting parameters and other options associated with megafunctions. For example, it would be desirable to have a mechanism that allowed the rich parameterization available with AHDL to be available for use with other Hardware Description Languages, so that megafunctions written in such other languages could be fully parameterized.
The present invention provides software modules, referred to herein as xe2x80x9cplug-ins,xe2x80x9d which associate with megafunctions written in any Hardware Description Language to provide rich parameterization. To the user, the plug-ins present an interface (sometimes referred to as a xe2x80x9cwizardxe2x80x9d) allowing selection or setting of any number of important parameters for a particular megafunction. To the design compiler, parameterized megafunctions instantiated via a plug-in appear to be a non-parameterized functions of a type that may be easily handled (by, for example, VHDL and Verilog compilers). Plug-ins xe2x80x9cplug intoxe2x80x9d a compiler or an application associated with the compiler, sometimes referred to as a xe2x80x9cplug-in manager.xe2x80x9d The plug-in manager creates compilable files from user-defined parameter settings passed by the plug-ins.
One aspect of the invention pertains to the operation of a plug-in or related application for setting options for a parameterized functional block of an electronic design. The operation may be characterized as follows: (a) prompting a user, via a user interface, to select settings for one or more options; and (b) packaging settings selected by the user in a file that can be compiled or used to generate a compilable functional block for the electronic design. Note that sometimes the option settings must be provided to allow the parameterized functional block to be compiled to an unambiguous circuit block forming part of the electronic design. In other cases, the functional block can be compiled, but the user is constrained to use default parameter settings unless presented with options via a method such as this invention. After packaging the settings, the plug-in system may provide the file to a compiler or an application that uses the settings contained in the file to generate the compilable functional block.
Usually, though not necessarily, the parameterized functional block is provided in a Hardware Description Language such as VHDL, Verilog, or AHDL. The HDL code for the parameterized functional block contains a parameter block identifying parameters that can be set to specific values by the user. The setting options may be of various types. Examples include parameter values (e.g., bus widths, buffer sizes, etc. from an HDL parameter block), the identification of which ports to use in the parameterized functional block, and connections between two or more functional blocks. Further, the user interface may allow the user to select one of two or more parameterized functional blocks that are interchangeable in the electronic design. For example, the user may be given the option of choosing one buffer with a single clock for synchronizing reading and writing or a second buffer with separate clocks for read and write operations.
The packaged user-selected settings for the parameterized functional block may be provided in a particular format required by the compiler or a manager application associated with the compiler. Such format may require hand shaking information for communications between a first entity (e.g., a plug-in) that creates the file and a second entity (e.g., the compiler or manager application) that receives the file. The file format may also allow for data specifying a symbolic representation of the parameterized functional block and associated user selected settings. Such symbolic representation may be a schematic that can be edited by an EDA schematic editor, for example.
Another aspect of the invention pertains to the operation of a plug-in manager or similar application. The operation involves providing a xe2x80x9ccompilable variationxe2x80x9d of parameterized functional blocks for electronic designs. This compilable variation, when used with associated parameterized functional blocks, allow the compiler to create unambiguous circuit blocks forming parts of electronic designs. Typically, both the variations (typically provided in xe2x80x9cvariation filesxe2x80x9d) and the functional blocks are embodied as HDL code. Without the information provided in a variation file, the parameterized functional block code might not be compilable to an unambiguous circuit design.
A plug-in manager should be able to handle information from many different plug-ins, each associated with different functional blocks. To emphasize that the manager can handle various plug-ins, the operation of the manager or related application may, in accordance with this invention, be characterized as follows: (a) receiving a first set of option settings containing user-selected settings for a first parameterized functional block; (b) generating a first compilable variation file specifying the first set of option settings; (c) receiving a second set of option settings containing user-selected settings for a second parameterized functional block; and (d) generating a second compilable variation file specifying the second set of option settings. When the first variation file is compiled with the first parameterized functional block, a first unambiguous circuit block is formed and when the second variation file is compiled with the second parameterized functional block, a second unambiguous circuit block is formed. Typically, the manager handles the first and second sets as separate projects, rather than via batch processing.
As mentioned, the variation file is typically provided as HDL code. Thus, it includes the user-specified options for a functional block in appropriate HDL format. The variation file must also tell the compiler how it is associated with the underlying or base parameterized functional block file. To this end, the variation file identifies the associated parameterized functional block (typically by name) and maps variables (by name) from the variation file to the parameterized functional block. The manager may generate, in addition to the variation file, a xe2x80x9cdeclaration filexe2x80x9d specifying an interface for the generated variation of the parameterized functional block. Many conventional compilers require such declaration files.
Another aspect of the invention pertains to apparatus for implementing the plug-ins and plug-in managers of this invention. Such apparatus may take the form of a computer or computational system. It may contain one or more processors configurable by instructions and/or data provided from one or more memory elements coupled to at least one processor. In the case of a plug-in, the apparatus should also provide a user interface (for providing selection options in the form of a wizard for example) via a display coupled to at least one processor. Often the apparatus will include one or more plug-ins, a plug-in manager and a compiler. The plug-in manager and the compiler may be tightly integrated. The apparatus may additionally house or have easy access to a library of parameterized functional blocks. Note that any of these entities may exist as a stand-alone functionality.
These and other features and advantages of the present invention will be described in detail below with reference to the associated drawings.